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Main Page
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Chipset Design
Digital ASIC and FPGA Design (RTL
coding, synthesis, floorplanning, place & route, STA, timing closure, ...)
Verification (testbench generation,
toplevel verify, emulation, FPGA prototyping, ...)
Analog and RF ASIC Design (schematic
editing, simulation, full custom layout, ...)
Mixed Signal ASIC Design
SOC and IP Design
XMXM Solutions® adopts and inherits Synopsys® IC Compiler©, the next-generation physical
design system — is architected to solve toda'ys emerging design challenges. As the
centerpiece of Synopsys® Galaxy Design Platform 2005®, IC Compiler© provides a comprehensive,
convergent solution with the most complete support for physical implementation from
netlist to GDSII. IC Compiler© unifies physical synthesis, clock tree synthesis,
routing, yield optimization, and sign-off correlation to deliver unmatched design
performance and designer productivity.
The Challenge
Driven by advancing silicon
technology, design challenges continue to multiply. Given the dynamics of a global
consumer-focused market, designer efficiency is also needed as never before. Physical
design today is far more complex than a few silicon generations ago. Interconnect
challenges, which started to dominate a few years ago, are far more complex today.
Design sizes are much larger, and potentially have more “long” routes. Resistance
variation across routing layers has increased two-to-three-fold. The number of routing
obstructions in the form of macros has increased ten-fold. Via resistance can be
two-to-three times the wire resistance. Complex clocking is pervasive and severely
destabilizing to overall interconnect management. Advanced silicon processes and
design variations now require much closer coupling between accurate timing sign-off
and implementation. And yield can no longer be treated as an afterthought: it must
be incorporated into the design process.
Current generation place-and-route solutions
— architected in late 1990’s — integrate physical design into a single executable.
However, these solutions have limited horizons because placement, clock tree synthesis
and routing are separate, disjoint steps. Additionally, yield optimizations and
timing sign-off are also separate steps, and are treated as "post-process". These
challenges require a new physical design solution.
Design Platform
Concurrent Physical Design
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The Solution
IC Compiler© — the
next-generation physical design system — is architected to solve today’s emerging
design challenges. It transcends current generation place-and-route tools by enabling
concurrent physical design.
As the first-ever physical design solution to unify
physical synthesis, clock tree synthesis, routing, yield optimization, and sign-off
correlation, IC Compiler© delivers unmatched design performance and designer productivity.
Key Features and Benefits
Extended Physical Synthesis (XPS©) extends physical synthesis
to full place and route. XPS technology unifies physical synthesis, clock tree synthesis
and routing to dramatically improve interconnect management. This provides better
time to results and quality of results in overall timing, area, power, SI and yield.
Sign-off Driven Design Closure closely couples Galaxy’s gold-standard sign-off tools
— PrimeTime® and Star-RCXT™ — with physical implementation for dramatically reduced
time to closure. By running sign-off incrementally to close on critical timing areas,
IC Compiler© is able to maintain fast throughput with high accuracy. These innovations
enable designers to achieve higher predictability, eliminate costly design margins
and achieve faster time to final results. Design for Yield (DFY) brings first-of-a-kind
innovations for yield loss prevention and recovery to the Galaxy Design Platform©.
In IC Compiler, these DFY innovations enable concurrent optimization for yield,
timing, area, power, routability, and signal integrity. By coupling these DFY innovations
with Synopsys® industry-leading design for manufacturing solutions, designers can
address the sources of defects throughout the flow.
Additional features round out
complete support for physical design Physical design-for-test optimization Comprehensive
low-power functionality Hierarchical and flat floorplanning Automatic macro placement
Power network design Chip finishing support TCL support throughout the flow PrimeTime-style
analysis TrueVue photorealistic visualization
Contact us for more information about the Hardware Designs Solutions. |
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